Techniques to embed SiGe source/drain regions have been used for CMOS devices to increase compressive stress in the channel region of PMOS devices to improve device performance by raising hole mobility. In such process flows, following gate stack and source/drain formation, a cavity is formed in the source/drain regions of the PMOS device. Cavity formation is generally accomplished by a multi-step dry etch process, followed by a wet etch process.
The first dry etch step is a first anisotropic dry etch used to etch through a deposited hardmask layer (e.g., silicon nitride) to begin etching of a cavity in the substrate (e.g., silicon), followed by an isotropic dry lateral etch (dry lateral etch) that expands the cavity including laterally toward the MOS transistor channel, followed by a second anisotropic dry etch to define the bottom wall of the cavity.
The multi-step dry etch is generally followed by a wet crystallographic etch which forms a “diamond-shaped” cavity. The wet etchant for the crystallographic etch has crystal orientation selectivity to the substrate material, such as an etchant comprising tetramethyl ammonium hydroxide (TMAH), which is used to etch the substrate beginning with the U-shaped recesses provided by the multi-step dry etch processing. During the wet crystallographic etching process, the etch rate of the <111> crystal orientation is less than that of other crystal orientations such as <100>. As a result, the U-shaped recesses become diamond-shaped recesses.
FIG. 1A is a depiction showing an in-process PMOS transistor 150 immediately after completing multi-step dry cavity etch processing showing the resulting SiGe-to-gate edge distance (S2G) that would result as defined by the then-present cavity dimensions. The PMOS transistor 150 is shown having a gate stack including a metal gate electrode 115 and a Hi-K dielectric 120 on a substrate 125 such as silicon, with a sidewall spacer 130 on the walls of the gate stack and a hard mask layer (e.g., silicon nitride) 135 on the gate electrode 115. Other parameters shown in FIG. 1A include the spacer width (SPW) which extends to the outer edge of the sidewall spacer 130. Due to slight undercutting during dry cavity etching, S2G is shown being somewhat less than SPW.
FIG. 1B shows a depiction of an in-process PMOS transistor 150′ after the wet crystallographic cavity etch forms diamond-shaped recesses. The S2G is shown to decrease compared to the S2G shown in FIG. 1A. The depth to tip of the diamond-shaped recesses is shown as d1, and the depth of the bottom wall is shown as d2.
Following the wet crystallographic etch, SiGe is grown epitaxially with in situ boron doping in the diamond-shaped recesses to form the PMOS embedded SiGe source/drain regions. The embedded SiGe regions should be spaced closely enough to the outer edge of the PMOS transistor channel so that they impart a high amount of compressive stress to the channel. However, the SiGe regions should not be too close to the outer edge of the PMOS transistor channel so that dopant diffusion from the in-situ doping in the SiGe overruns the PMOS channel and changes the channel doping, and as a result alters the PMOS threshold voltage (Vt).
As a result, the electrical parameters for the PMOS transistor having embedded SiGe sources and drains, especially the PMOS Vt, are known to have a strong dependence on S2G. Accordingly, good control of S2G is needed to help control the Vt for PMOS transistors.
The value of S2G can depend on a plurality of factors that are each generally not well controlled wafer-to-wafer or run-to-run (e.g., lot-to lot), including the incoming silicon oxide thickness from various oxidation steps, the amount of spacer (e.g., a silicon nitride spacer) remaining prior to SiGe processing, the thickness of the spacer material used to define the amount of S2G, and the etch rates of the subsequent SiGe dry etch steps and wet etch step used to form the cavity before SiGe epitaxial growth. Good S2G control is therefore difficult to achieve, both wafer-to-wafer and run-to-run.